As a mobile communication medium such as a cell phone becomes sophisticated in performance and is miniaturized, high capacity and high performance level are required of an electrostatic capacity element used in a semiconductor integrated circuit for communication use. Such an electrostatic capacity element includes a lower electrode as a first conductive layer, an upper electrode as a second conductive layer, and a dielectric layer sandwiched between the lower electrode and the upper electrode. From among the elements, a metal-insulator-metal (MIM) capacitive element having metal electrodes, in particular, has a low parasitic capacitance and a low parasitic resistance and may achieve high performance.
Japanese Laid-open Patent Publication No. 2005-79513 discusses a technique of a semiconductor device including an MIM capacitive element that includes a lower electrode, an upper electrode having an area larger than an area of the upper electrode, and a dielectric layer. In accordance with the disclosure, an insulating layer is deposited on a top surface and a side wall of the upper electrode to maintain insulation on the dielectric layer.
Opening operations of opening via holes in the upper electrode and the lower electrode of the MIM capacitive element in the semiconductor device are performed separately. Since the opening operation needs a plurality of mask formation operations, a manufacturing process has an increased number of operations. To decrease manufacturing operations, the opening operations are preferably performed on the upper electrode and the lower electrode at the same operation. If such an opening operation is performed, the upper electrode may be overetched because of a difference in thickness of the electrodes, and the dielectric layer may be damaged.